About

Experienced team delivering successful tapeout's in RISCV, AI, DSP domain since 2018.
Skills: RTL, Verification, Validation, Timing Closure, ECO.
Domain: RISCV, AI, DSP, Networking.
ASIC: Tapeouts in technodes from 180nm to 7nm
FPGA: Worked with Xilinx and Altera FPGA's